A level shifter is a circuit that converts an input signal having the voltage amplitude of VDD1 into an output signal having the voltage amplitude of VDD2. Typically, the amplitude is converted by fixing the lower potential side, typically referred to as VSS, and converting the potential at the higher potential side. Level shifters are widely used in integrated circuits where more than one application circuit, each having different amplitudes, are integrated together.
A common application is shifting the voltage of a signal transferred between an input/output (“IO”) circuit and a core circuit. Historically, the IO operation voltage was compatible with the core operation voltage. However, with the shrinking of the VLSI circuit, the operation voltage of the core circuit continues to be reduced while the IO operation voltage stays relatively steady, so that currently, the core operation voltage is typically much lower than the IO operation voltage. For example, in deep sub-micron technology, the core operation voltage has dropped to about 0.9 to 1V, and the IO operation voltage stays at about 2.5V to 3.3V. Therefore a signal needs to be level shifted before it is sent from a core circuit to an IO circuit or from an IO circuit to a core circuit. Usually, VSS is set at ground potential or 0V, and VDD is set at 0.9 to 1V for the core and 2.5 to 3.3V for the IO. In other instances, VSS may be set to a higher voltage level or a negative voltage level. In such cases, only the level of VDD need be adjusted. In other instances, the level of VSS is adjusted, or the levels of both VSS and VDD are adjusted.
FIG. 1 illustrates a conventional digital level shifter circuit. Nodes 2 are power supply nodes at a power supply voltage VDD, which is a core operation voltage. Nodes 26 are power supply nodes at a power voltage VDDH, which is an IO operation voltage and is higher than VDD. Node 12 is an input node and node 30 is an output node. When the input signal at node 12 switches from 0 (0 volt) to 1 (VDD), the voltage at node 14 changes from VDD to 0V since pMOS 4 and RMOS 8 form an inverter. The gate voltage of the transistor 20 at node 28 also changes to 0 volt, causing the nMOS transistor 20 to cut off. The pMOS transistor 6 and nMOS transistor 10 form another inverter, so that the voltage at node 16 changes to VDD, causing transistor 18 to conduct. The voltage at node 32 is pulled down so that pMOS transistor 24 conducts. The output voltage at node 30 is pulled up to VDDH by transistor 24.
If input signal at node 12 switches from 1 to 0, voltage at node 14 changes to 1, causing transistor 20 to conduct and the output voltage at node 30 is pulled down. Simultaneously, the voltage at node 16 switches to 0V, causing transistor 18 to cut off, and the voltage at node 32 is pulled up by the pMOS transistor 22. Transistor 24 is cut off due to the high gate voltage at node 32, and the voltage at output node 30 is eventually pulled down to 0 volt. Therefore, the input signal with amplitude of VDD is shifted to an output signal with amplitude of VDDH.
The circuit illustrated in FIG. 1 performs well when VDD is higher than the threshold voltage of the transistor 18 and 20 with adequate margin. However, when a VLSI circuit gets smaller, the gate oxide of the core CMOS gets thinner. The supply voltage of the core CMOS is also lowered to protect the gate oxide from damage and the hot carrier effect. When VDD is dropped to a level close to the threshold voltage of nMOS 18 and 20, the conventional low-to-high level shifter becomes slow. To explain in detail, assume the input voltage at node 12 is VDD, so that transistors 20 and 22 are off and transistors 18 and 24 are on. When the input voltage at node 12 is switched to 0V, the state of the transistor 20 changes from off to on so that it starts to pull down the voltage at node 30. The drain current of a transistor can be expressed as:Id=k*[2(Vgs−Vt)Vds−Vds2]  [Eq. 1]where k is a device parameter, Id is the drain saturation current of the transistor, Vgs is the voltage difference between the gate and source, and Vt is the threshold voltage of the transistor. It is observed that the current is directly related to Vgs−Vt. If the voltage VDD at node 28 is close to Vt, the drain-source current Id is very small, and it is hard for transistor 20 to pull down the output voltage at node 30, so that the level shifter is slow and high frequency response is degraded. One of the common solutions is to increase the aspect ratio W/L to increase the transistor 20's drain-source current. This is because k can be expressed as:k=½μnCox(W/L)  [Eq. 2]where μn is the electron mobility, Cox is the capacitance per unit area of the capacitor between the gate electrode and the channel, W is the channel width, L is the channel length, and W/L is the gate aspect ratio. When W/L increases, k increases and the Id increases. When the core circuit's operation voltage continues to drop, W/L needs to be further increased to compensate.
Since power supply voltage VDDH stays higher, the transistors 18, 20, 22 and 24 are normally thick oxide transistors so that they can withstand higher operation voltages without being damaged. However, the thick oxide transistors also have higher threshold voltages, making the threshold voltage closer to VDD. If the VDD is equal to or lower than the threshold voltage of transistors 18 and 20, the transistors cannot be turned on, so that the level shifter will malfunction. Therefore, there is the need for a level shifter that has high performance even when operated at a very low core operation voltage.